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Sithole, Ernest, McClean, Sally, Scotney, Bryan, Parr, Gerard 
ORCID: https://orcid.org/0000-0002-9365-9132, Moore, Adrian, Bustard, Dave and Dawson, Stephen
(2011)
Quality of service monitoring strategies in service oriented architecture environments using processor hardware performance metrics.
IGI Global.
Abstract
The sharp growth in data-intensive applications such as social, professional networking and online commerce services, multimedia applications, as well as the convergence of mobile, wireless, and internet technologies, is greatly influencing the shape and makeup of on-demand enterprise computing environments. In response to the global needs for on-demand computing services, a number of trends have emerged, one of which is the growth of computing infrastructures in terms of the number of computing node entities and the widening in geophysical distributions of deployed node elements. Another development has been the increased complexity in the technical composition of the business computing space due to the diversity of technologies that are employed in IT implementations. Given the huge scales in infrastructure sizes and data handling requirements, as well as the dispersion of compute nodes and technology disparities that are associated with emerging computing infrastructures, the task of quantifying performance for capacity planning, Service Level Agreement (SLA) enforcements, and Quality of Service (QoS) guarantees becomes very challenging to fulfil. In order to come up with a viable strategy for evaluating operational performance on computing nodes, we propose the use of on-chip registers called Performance Monitoring Counters (PMCs), which form part of the processor hardware. The use of PMC measurements is largely non-intrusive and highlights performance issues associated with runtime execution on the CPU hardware architecture. Our proposed strategy of employing PMC data thus overcomes major shortcomings of existing benchmarking approaches such as overheads in the software functionality and the inability to offer detailed insight into the various stages of CPU and memory hardware operation.
| Item Type: | Book |
|---|---|
| Faculty \ School: | Faculty of Science > School of Computing Sciences |
| UEA Research Groups: | Faculty of Science > Research Groups > Smart Emerging Technologies Faculty of Science > Research Groups > Cyber Security Privacy and Trust Laboratory |
| Depositing User: | Pure Connector |
| Date Deposited: | 24 Sep 2016 01:04 |
| Last Modified: | 14 Mar 2023 08:39 |
| URI: | https://ueaeprints.uea.ac.uk/id/eprint/60447 |
| DOI: | 10.4018/978-1-61350-432-1.ch005 |
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