Automated technique for high-level circuit synthesis from temporal logic specifications

Dowsing, R. D., Elliott, R. and Marshall, I. (1994) Automated technique for high-level circuit synthesis from temporal logic specifications. IEE Proceedings: Computers and Digital Techniques, 141 (3). pp. 145-152. ISSN 1350-2387

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Abstract

A general-purpose strategy for the synthesis of digital circuits from high-level behavioural specifications expressed in the temporal-logic language Tempura is described. This strategy has been implemented as a synthesis tool called AST, and the application of AST to part of the specification for an error-encoder circuit is examined

Item Type:	Article
Faculty \ School:	Faculty of Science > School of Computing Sciences
Depositing User:	Vishal Gautam
Date Deposited:	08 Mar 2011 08:43
Last Modified:	15 Dec 2022 02:07
URI:	https://ueaeprints.uea.ac.uk/id/eprint/22293
DOI:	10.1049/ip-cdt:19941005

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