VLIW: a case study of parallelism verification

Adir, Allon, Arbetman, Yaron, Dubrov, Bella, Lichtenstein, Yossi, Rimon, Michal, Vinov, Michael, Calligaro, Massimo A., Cofler, Andrew and Duffy, Gabriel (2005) VLIW: a case study of parallelism verification. In: Proceedings of the 42nd annual Design Automation Conference, 2005-06-01.

Full text not available from this repository.

Abstract

Parallelism in processor architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. In this paper we report on the verification of a Very Large Instruction Word processor. The verification team used a sophisticated test program generator that modeled the parallel aspects as sequential constraints, and augmented the tool with manually written test templates. The system created large numbers of legal stimuli, however the quality of the tests was proved insufficient by several post silicon bugs. We analyze this experience and suggest an alternative, parallel generation technique. We show through experiments the feasibility of the new technique and its superior quality along several dimensions. We claim that the results apply to other parallel architectures and verification environments.

Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: processor verification,vliw,test generation,parallelism,functional verification
Faculty \ School: Faculty of Social Sciences > Norwich Business School
Related URLs:
Depositing User: Elle Green
Date Deposited: 06 Jul 2012 08:46
Last Modified: 22 Apr 2020 09:09
URI: https://ueaeprints.uea.ac.uk/id/eprint/39093
DOI:

Actions (login required)

View Item View Item