Test program generation for functional verification of PowerPC processors in IBM

Aharon, Aharon, Goodman, Dave, Levinger, Moshe, Lichtenstein, Yossi, Malka, Yossi, Metzger, Charlotte, Molcho, Moshe and Shurek, Gil (1995) Test program generation for functional verification of PowerPC processors in IBM. In: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference, 1995-06-01.

Full text not available from this repository.

Abstract

A new methodology and test program generator have been used for the functional verification of six IBM PowerPC processors. The generator contains a formal model of the PowerPC architecture and a heuristic data-base of testing expertise. It has been used on daily basis for two years by about a hundred designers and testing engineers in four IBM sites. The new methodology reduced significantly the functional verification period and time to market of the PowerPC processors. Despite the complexity of the PowerPC architecture, the three processors verified so far had fully functional first silicon. 1 Introduction A new methodology and tool for functional test program generation has been used for several IBM PowerPC processors. The functional verification period and the processors time to market were reduced. Only one fifth of the simulation cycles needed to verify a RISC System/6000 processor with a previous generator was needed with the new methodology for a PowerPC processor. The new g...

Item Type: Conference or Workshop Item (Paper)
Faculty \ School: Faculty of Social Sciences > Norwich Business School
?? NBS-LON ??
University of East Anglia > Faculty of Social Sciences > Research Groups > Innovation, Technology and Operations Management
Related URLs:
Depositing User: Elle Green
Date Deposited: 06 Jul 2012 11:07
Last Modified: 25 Jul 2018 02:04
URI: https://ueaeprints.uea.ac.uk/id/eprint/39098
DOI:

Actions (login required)

View Item